Modeling Approach

The Steps of My Approach to Behavioral Model Creation

R. Peruzzi Consulting, Inc.


  •  From a schematic or symbol, automatically create the shell of a Verilog or VHDL (-AMS) model, with I/O matching the schematic and a few other starting points.
  • Study the schematic and interview its designer to develop a description of the circuit behavior.  This description becomes part of the model, within comments, and includes narrative text, tables and ASCII waveforms, equations and diagrams.
  • The designer blesses the description, and is obligated to notify me (or the model's owner once I'm gone) of any changes to behavior (gain, BW etc.) or pinout changes.  There is no good way to automatically force the designer to comply; it is a matter of due diligence.
  • Study the verification plan and interview the lead verification engineer along with the circuit designer to decide which behaviors of the circuit are to be included in the model:
  • For example, we may decide to not model the fixed bandwidth of an amplifier, eliminating a differential equation and thus speed up simulation time as long as verifying overall signal path bandwidth is not part of the verification plan.
  • Continuing that same example, if the bandwidth is digitally controlled via a state machine, and verifying that state machine is part of the verification plan, the model must verify correctness of the digital control.  Actually, digital verification of the external state machine within the AMS model is more reliable than analog verification because it is more easily automated and doesn't rely on human eyeballs.
  • Other decisions may be whether to model the power supply as an electrical voltage or simplify it to a logic wire.  Again, simplifying the job of the analog solver speeds up the simulation.
  • The lead verification engineer and designer bless the plan and it becomes part of the model description, within the model.


  • Writing the code from the description is the easy part. But every model must be validated before the job is done.  Each model is validated on a testbench schematic separate from the full chip environment.  Common sense dictates the model be validated by someone other its author, but the circuit designer shouldn't need to learn the modeling language or how to use a new simulator to do so.  Here is my approach:


  • Model designer creates a testbench schematic instantiating the symbol for the device under test (DUT) and a symbol for a driver-monitor (DMON).  All pins of the DUT connect to the DMON
  •  Validation answers two questions:
  1.  Does the model match the circuit, or more precisely, does the model match the model plan blessed by the designer and lead verification engineer?
  2. Does the model respond correctly to all input sequences, including illegal combinations and bad logic?
  • To answer the first question, the circuit designer describes a pattern of waveforms and input control sequences to the model designer.  The model designer creates the DMON code to drive that pattern.  DMON can drive either the transistor level schematic or the model.  Model designer simulates both model and schematic, debugs model and tunes it to "match" schematic as nearly as necessary by the model plan. Model designer delivers the testbench and an Analog Artist State cellview to the circuit designer.  Circuit designer acknowledges that the model is valid versus the schematic.
  •  Note that the AMS simulator inserts interface elements as necessary when the DMON is driving transistor-level schematics and when (if applicable) the model is treating the power supply voltage as a logic input
  • To answer the second question, there is an infinite number of legal and illegal combinations of input controls and waveforms.  The model designer comes up with a set of input sequences to exercise all the model's operating modes and fault detecting code.  Design engineer and lead verification engineer may critique and request other input sequences.  This part of validation is very important and tends to reduce the number of problems occurring in full chip simulation.  It is based on experience and intuition.